2026年8月27日上午，由bat365正版唯一官网、集成电路高精尖创新中心、bat365正版唯一官网国家集成电路产教融合创新平台、集成电路科学与未来技术北京实验室和“111”计划联合主办的“未名·芯”论坛系列讲座第七十七期在微纳电子大厦103报告厅成功举办。本期论坛邀请韩国汉阳大学ERICA校区Sang-Hoon（Sean）Shin教授作题为《Thermal Management and Reliability of Advanced Semiconductor Packaging: From Transistor Self-Heating to 2.5D/3D Heterogeneous Integration》的学术报告。报告由bat365正版唯一官网吴恒副教授主持。
随着人工智能和高性能计算芯片的功耗密度持续上升，制约系统性能提升的关键因素已逐渐从单纯的晶体管速度转向热量能否被及时、有效地导出。Shin教授结合其在晶体管可靠性、先进封装以及人工智能硬件热管理领域的研究与产业经历，从器件、互连、封装到系统多个层次，系统介绍了先进半导体系统面临的热管理和可靠性挑战。
报告首先从器件层面的自热效应展开。Shin教授指出，在FinFET及环栅晶体管等先进器件中，几何尺寸的缩小以及低热导率介质材料的广泛使用，使沟道产生的热量更难扩散。由此引起的局部温升不仅影响器件性能，还会加速偏置温度不稳定性、热载流子退化、栅介质击穿以及互连电迁移等可靠性问题。因此，结温正在成为连接器件退化、封装架构和系统散热设计的关键指标。
随后，报告将讨论拓展至后端互连和封装层面。随着互连层数增加，介质材料、金属互连、热界面材料、封装盖板及散热器共同构成复杂的热传输路径，封装设计对芯片结温的影响日益突出。Shin教授强调，热管理不能仅在设计末期通过增加散热部件加以补救，而应在器件和系统设计的早期阶段，将电学性能、功耗分布、热阻以及可靠性协同考虑。
在2.5D集成方面，Shin教授以高性能计算芯片与HBM集成为例，分析了高功率逻辑芯片与温度敏感的存储芯片相邻布置所引发的热耦合和非对称热点问题。由于DRAM的刷新和数据保持特性对温度较为敏感，局部温升可能进一步影响系统性能与能效。在3D异质集成中，多层有源芯片的垂直堆叠显著缩短了互连长度，却也使内部层的散热路径受到限制。玻璃基板等新型封装材料还会改变系统的热机械特性，引入翘曲、热膨胀系数失配以及互连应力等新的可靠性挑战。
针对上述问题，Shin教授进一步介绍了热测试载具（Thermal Test Vehicle，TTV）方法。通过采用可编程加热器、温度传感器及能够复现实际功率分布的测试平台，可以在早期评估热界面材料、封装盖板、均热板、冷板以及液冷、浸没式冷却等方案的效果，并获得支撑热—可靠性协同设计所需的实验边界条件。报告还结合晶圆级人工智能训练硬件和高产量消费类芯片封装案例，说明了测试、建模与工程验证之间建立闭环的重要性。
报告结束后，现场师生围绕先进器件自热效应的测量与建模、逻辑芯片与HBM之间的热耦合、热测试载具与真实芯片的一致性，以及不同冷却技术的适用场景等问题与Shin教授进行了深入交流。Shin教授结合产业实践与科研经验作了细致解答，现场讨论气氛热烈。
本次报告贯通了从晶体管自热、后端互连到2.5D/3D异质集成的完整技术链条，展示了热管理与可靠性设计在先进人工智能芯片中的重要作用。报告加深了师生对先进封装热问题及其失效机理的认识，也为开展跨越器件、封装和系统层次的热—可靠性协同研究提供了有益启发。
个人简介：
Sang-Hoon (Sean) Shin is an Assistant Professor in the Department of Electronic Engineering at Hanyang University ERICA, Republic of Korea, where he directs the Advanced Reliable Component Laboratory (ARC Lab). His research spans semiconductor reliability from front-end-of-line (FEOL) device physics to back-end-of-line (BEOL) interconnects, advanced packaging, and system-level thermal management, with emphasis on self-heating, thermal test vehicle (TTV) platforms, 2.5D/3D heterogeneous integration (CoWoS, HBM, glass substrates), and device-to-system reliability engineering for AI hardware.
Prior to joining Hanyang University in March 2025, he spent eight years in the U.S. semiconductor industry. At Tesla (2022-2025), he was a Semiconductor System Engineer responsible for package development and AEC-Q qualification of the AI5 Full Self-Driving SoC and the Dojo wafer-scale training system (System-on-Wafer/CoWoS). At Apple (2020-2022), he was the SoC Package Integration Reliability Engineer directly responsible (DRI) for reliability of the first Apple Silicon (M1/M2) Mac products. At Intel (2018-2020), he worked as a CMOS Reliability R&D Engineer, and he began his career as a Postdoctoral Researcher at the IBM T.J. Watson Research Center (2017-2018) for ultra-low-k BEOL reliability.
He received his Ph.D. in Electrical and Computer Engineering from Purdue University in 2017 under Prof. Muhammad A. Alam, with a dissertation on self-heating of confined-geometry transistors and integrated circuits, an M.S. from the University of Tokyo (Prof. Shinichi Takagi), and a B.S. in Electronic Engineering and Computer Science from Hanyang University.
He has authored more than 50 publications, including 18 first-authored papers - six at IEDM and IRPS, with first-authored IEDM papers in four consecutive years - and holds two granted U.S. patents.
